1. Technical Field
The present invention pertains to an integrated circuit (IC) in general, and more particularly to a power source detecting circuit in an IC that receives two power sources. One is an IC power source, and the other is an IC data power source. The embodiment of the present invention provides a mechanism to automatically adjust the IC to operate at an appropriate data power level.
2. Background Art
In a use of a Dynamic Random Access Memory (DRAM), two different power sources are normally provided to the DRAM. One power source usually named VDD is a DRAM operating power source; the other power source usually named VDDQ is a DRAM data power source. The two power sources may not operate at a same power level. For instance, a typical DRAM operating power source VDD is at 2.5 volts (2.5 V), and its cooperating data power source VDDQ can be at 2.5 volts or at 1.8 volts depending on a use of the DRAM. To be able to ensure that VDD is ready for a DRAM to function normally, a VDD power level detecting circuit is built into the DRAM as depicted in FIG. 6, and FIG. 7. FIG. 6 demonstrates the VDD power level detecting circuit in a block diagram 600. In FIG. 6, an input VDD and an output node A of the power detector 610 are a DRAM operating power source and an output indicating node respectively. As a change state of the output signal A occurs, the DRAM catches this signal and starts to operate at this given power source VDD. FIG. 7 provides an instance of the VDD power level detecting circuit depicted in the block diagram in FIG. 6. In FIG. 7, as soon as the output signal A changes states from logic 1 (logic high) to logic 0 (logic low), the DRAM internal circuit is ready to operate under the power source VDD. The following paragraph provides a detail description to FIG. 7.
As in an initiation of the power source VDD, the voltage level of VDD rises from zero to its steady state voltage level; let's say 2.5 volts. By carefully choosing resistance values of the resistors 710, 720, and 730, before VDD reaches its steady state voltage level, the output signal A is at logic 1. It is noted that at this state, a voltage at a node between resistor 710 and resistor 720 is not enough to turn on transistor 750 so that via resistor 730, the output signal A is pulled up to logic 1. As the voltage level of VDD increases and reaches its steady state voltage level, 2.5 volts, the voltage between resistor 710 and resistor 720 that supplies to the Gate terminal of the transistor 750 is big enough to turn on the transistor 750. Thereby, the transistor 750 is turned on, and the voltage level of the output signal A is pulled down to logic 0. As soon as the output signal A changes states from logic 1 to logic 0, the rest of the DRAM circuit receives the indication and starts to operate at this VDD voltage level.
The current VDD power source detecting scheme works fine in ensuring a DRAM to work at a good power source. Not like VDD power source, however, instead of having a power detecting circuit, a fixed power level is preset to a DRAM data power source during a DRAM fabrication. It is not possible for a DRAM with 2.5 volts preset data power source to work at a 1.8 volts data power level, and vice versa, after the DRAM comes out from a manufactory. The preferred embodiment of the present invention provides a method as well as a circuitry to allow a DRAM automatically detecting an environment VDDQ data power level and self-adjusting to operate at a provided VDDQ data power level properly.
With the present invention, an integrated circuit, such as a DRAM, works flexibly in various data power sources without tying up to a fixed data power source after manufacture. This feature greatly increases IC usability and reduces IC stock problems. For the foregoing reasons, there is a need for a data power level auto-configure circuit that is built in an IC and that can be inexpensively manufactured.